Cost-Efficient Fault-Tolerant Router Design for 2D-Mesh Based Chip Multiprocessor Systems
نویسندگان
چکیده
In this paper, a cost-efficient fault-tolerant router design, called 20-Path Router (20PR) architecture, is proposed to reduce the impacts of faulty routers for 2D-mesh based chip multiprocessor systems. The 20PR consists of two fault-tolerant circuits: 1) a Builtin Self-Test and Self-Diagnosis (BIST/SD) circuit to detect and locate faulty FIFOs and MUXs, and 2) a Fault-Isolation (FI) circuit to isolate the faults for operations of the faulty routers. The BIST/SD circuit can provide 97.79% fault coverage in FIFOs and MUXs and support at-speed testing with constant test patterns and constant test cycles. The BIST/SD circuit and the FI circuit cost only 13.54% area in the proposed 20PR design. Besides, according to the area and fault tolerance metric, the proposed 20PR can achieve at least 25.1% improvements in comparison with RoCo and FTDOR architectures.
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